Binary counting system



Jan. 2a, 1958 s. FIT-Z GERALD 2,821,638

BINARY COUNTING SYSTEM Filed June 15, 1956 2 Sheet s-Sheet 2 OUTPUTFLIP-FLOP SUPPLY D41 OUTPUT- h-C OUTPUT United States Patent ice BINARYCOUNTING SYSTEM Alan 5. FitzGerald, Mill Valley, Calif. Application June15, 1956, Serial No. 591,631"

19 Claims. (Cl. 307-88) This invention relates to electrical countingcircuits,

and more particularly to binary counting systems, such as those whichform the basis of digital computing apparatus.

type of electrical counting stage which is distinguished from the priorart in that no symmetrical relation is necessary between the pair offlip-flops in each stage,

whereby careful matching of tubes, resistors, transistors,

. or magnetic core devices is unnecessary.

Binary counting systems of the above mentioned character include, as theprincipal functional element, bi-stable electrical systems of the typecommonly referred to in In general a flip-flop may be the art, asflip-flops.

considered to be any electrical or other system which possesses theproperty of having two or more stable states of operation, which it iscapable of assuming-the maintaining under the same conditions ofenergization and without change in the circuitelements or connections.

Devices having this characteristic-are familiar in the art of mechanicalengineering and are referred to as toggle systems. Examples of analogouselectrical systems are the well known Eccles-Jordan electronic flipfiopand the magnetic amplifier type of flip-flop disclosed by the presentinventor in U. S. Patent No. 2,027,312.

All of the systems above adumbrated possess the additionalcharacteristic that they are capable of transfer from one of the saidconditions of stability, to the other, in response to a control impulseor signal of the appropriate nature.

The present invention is directed to the character of the said impulseor signal, and to the manner of response of the flip-flop thereto.

manifested by the type of electrical switch so nomenclated.

One of the most familiar examples of the toggle type of response is thatwhich is In the simplest form of toggle switch, on or off. ac-

tion, as desired, is obtained by actuating the switch in one or other oftwo different directions or senses.

Another type of manually operated toggle switch,. in-

volving structure additional to that included in the simple type abovecited, is identified by the description canopy or chain-pull type.

When a switch of this latter type is actuated successively, in a singlesense only, it gives, alternately on and off action. Types of relayswhich respond in this manner are well known and are sometimes called impulse relays. When relays of this type are repeatedly energized theywill alternately open and close the contacts. It is well known thatdevices capable of this kind of response form the basis of the binarysystems which are. the foundation of the digital computer art.

It is, accordingly, an object of my invention to provide a method andmeans whereby the basic type of electrical flip-flop, which acts in themanner of a simple toggle switch, may be given the more complexcharacteristics of the chain-pull type of toggle action. That is to say,my invention is a solution of the problem of deriving, from a systemwhich, basically, gives bi-lateral action in response to controlimpulses of bi-lateral sense, a system in-which each successive impulse,in a series thereof of unilateral sense, produces afresponse opposite insense to that which occurred as a result of the preceding signalimpulse. A

It is another object of my invention to provide a system It is a furtherobject of my invention to provide a binary element which, while it isapplicable generally, is particularly adapted to the use of magneticamplifier structure and thus especially suitable for use in applicationsin which magnetic amplifiers are for other reasons essential elements;as for example, in converting from an analogue computer of magneticamplifier type to a digital sealer.

Another object of my invention is to provide a typ of electricalcounting stage which is extremely positive in'its action with regard toreversal of state.

These and other novel'feat'ures which I believe to be characteristic ofmy invention will be set forth with particularity in the appendedclaims- My invention itself,

however, both as to its organization andmethod of operation, togetherwith further objects and advantages thereof, may best be understood withreference to the follow ing description taken'in connection with theaccompanying drawings, in which:

Fig. l is a schematic diagram illustrating the basic principle of myinvention;

Fig. 2 is an electrical circuit diagram illustrating an embodiment of myinvention utilizing flip-flops of magoutputs, since there isnosymmetrical relation therebe- In order to disclose and to describe theopertween. ation of my invention in the most direct and simple manner lhave omitted, in Fig. 1, conventional details of the structurepertaining to the flip-flops A and B since the precisenature of theseelements is not a primary feature of my invention.

My invention may be practised effectively with any type of bi-stableelement capable of remaining in one or other of two states of stability,one of these furnishing a substantially greater output than the other;and which can be caused to transfer from either of these two stablestates to the other by momentary application of signal impulses ofappropriate and differing sense.

For example the flip-flops A and B may comprise snapaction relays,electron discharge devices, semi-conductor and output, and windings orother receiving CiICllitjl ments to which, in the particular type offlip-flop em- Patented Jan. 28, E958 3 ployed; it is customarytto-applythe controlling signal impulses.

In the interest of brevity of text the condition of stability giving thelower value-of output will hereinafter be: referred to .as the fiop?state, and that giving the higher output, the flip. condition.. Inlikemanner-the:

action ofptransfer ifromflthe: lower toutputvcondition to'v thehighoutput state rwill besreferred toias flip= and the opposite actionfiop..

Letuit be-supposed, by :way of-example, in Fig; l, thatthe,.1fiip-flops. -A andtB .arexof avtype which may beacausedito flipand flop by. the momentary application ofxa- ;D.-C.;signal .1offreversible-polarity, as; for instance-s would;be..the 'caseiifthetflip-fiopsvA- and Biwerezsnap u action polarized relays-yer;magnetic-1amplifier:elementsi such.- as; those disclosed 1 in the abovecited:= U. S. :patent. Forpconveniencert in. explanation wetwill .refertOfithC! positive and 1 that which causes: the. -fiop' state as:negative.=

Rcferringiagainto Fig. 1, I show the. flip-flops- Az and B energized;with A'.-C, .ofnat suitable .frequency::from-- the source; 1;;threugh:binding poste -2,; 3 'and;12; .13:

I show also output binding posts 4, 5 at which the out? put. of zAeInaybeutilized; A710... operated; flip-'fiopst-in gencral linclude.rectifying elementsn This is the case for' example in Patent-2,027,312.:Accordinglya'outputufroini:

such devieestds' ,obtainable-teitherlbefore or= =after rectificationinr-thenfornr of- A;- C. or DsC. current as desired;

In gEigr lnfiipfiop A- delivers .itsroutput, at 1 binding, :posts:--

4, Sin the;fonn-of:D.+C;

L show; also rpeitainingio flip-flop A three: additional bindingrposts:6, =.7;. Bxandficont'rol -1elementsand 11.

Contrqlzelement :10 is :connected: to binding post 6, andi controlelement 11 to post 7. Binding post' ti -provides a common ;re.turnvfor.both -10,.and\11'.'

The control element 10 or 11' is to'bet understood to be-wthe;;flip,-flo p. element :which .receivesthe controlling impulsezorzsighali'ienergy applied for --the purpose of 1 causing the bi-stablesystem to transfer from one con-- ditionzofrstability'tothe others Forexample, electronic devices,-are customarily controlledby some form; ofI voltagerdrop producingldevice such as a resistor traversed by ;a,current ofv .variable; magnitude; other flip-flop devices such as,relays-lorhr'na'gnetic amplifiers maybecontrolledby-ampereeturnxproducing means suchias aflow of current in asuitable maghetizing winding.

Thus in; Fig.1 lythe, circuit, elements shown at ,10 and 11', are ,to;be understood: to :be controlling means: appropriatextouthe-type.of:1flipefiop used at Aland B. It: is further' to lie-understood;thatawhen: either of'theele--- ments:;-10 .or';l1 isrenerg'ized in'the senseindicated in Fig., 1 by an upward directed :arrov'v;v the control effectis exertedinua,directionisuchas totend to cause -the-fiip'- flopqA to,be flipped;,that; is;to say,-. to.'be; transferredfrom he; low 1current: state) :to the condition :of stability which gives the highercurrent output. The opposite effect is denoted by anrarrow pointingrdownwards.

Thus, as indicated by thet'directionto'f: the-arrows in the sense, ofthe resultant effectwill' be in l the -flop'dire'c- V tionr In otherwords,-if '10"preponderates--over-11;the flip-flop A-will assumezla'state- -such that a-current-ofsubstantial magnitude may be furnishedat --bin ding;posts 4, 5: Co'nvrselyyif 11 preponderates' over: 10. theHipflop A will assume the other-conditionof stability iriwhichthecurrentfurnishedwill be of a relativelylower magnitude.

Referring nowato thefiiii-fiop a rshow e binding; V posts-'14; 15;correspondifig; iri flip-11615 133 with tt andfl mayube. obtained. I-ShOW alSO- a .second. pair. of. bind-,.

ing posts 24 and 25 included in flip-flop B, from which energy may bewithdrawn, in alternating form, previous to the rectification procedurefor energizing binding posts 14, 15.

Whereas, in the case of flip-flop A it is only necessary that the flopcurrent-1 ber substantially lower than the flip current, a slightlydifferent characteristic is necessary in respect to flipdlop "B3 inthis'- case -it-- is desired that the output-currenL-both D,:C- ;Bbinding posts 14, 15, and A.-C. at binding posts 24, 25, in the flopcondition, be:-' reduced to approximately-zero.--

I show also, included'in the flipx-flop -B, .a pair of controlling means20'and 21, corresponding to the similar elements 10 and 11 of flip-flopA and likewise exerting effects in opposing sense as indicated by arrowsin the same manner as those pertaining to 10 and 11. I show binding:posts at- 17, 18;forproviding-connectionto the control meansa2ltt Inthetcase-of= thecontrolcircuit 20, in fiip-fiop-B,

' according to the operation of my invention, it is-not necessary*thatthe elfect-- exerted by 20. be'variabler Accordingly; in orde'r'to'make the diagramas-simple aspossible :I have omitted connectionsnecessary for supply ing:2(bwith1a current or-voltageof fixed magnitudeand" have;insteadgindicated by and insignia that this circuit.elementaisttobes'o energized.-

' In:the operation of "my invention the function of the flipflopaBl'isqa simple one-. It is required only, that-itrespondapositively', and -iri inv'erse sense; to the action of. A;thatiiti shall instantly fiipwhen A' fiops and hop when A flipss The:fiir'fifiop"A isircontrolleddirectly by -the incoming signals,:.whicharexassumed to-be unidirectional impulsesotfunchangingipolarity;delivered.atbinding posts 22, 23;

By .hypothesis bothof the flip-flops -A and B areassumedtato -.be:responsive-to control impulses -of alter- 'natelyn reversin'gsense' or.polarity; Accordingly; an

instrumentality 'is requir'ed which-willconvert the said uni-form 1pulse signals into 'efi'ects; applied to flip-flop A, of alternatelyreversing sense or polarity;-

ThiSxtl'GSlllU is robtained by an arrangement whereby both. ofrthecontrol elements 10 and '11 of the flip-flop A -aresimultaneouslyenergized" by the incoming pulse signalts. Thisiis'accomplished "by :providinga divided sig-' naliinputcircuit so th'at twoparallel paths" exist between bindingaposts- Ro and- 233 One-of theseincludes the t controbfnircuit.115and a-resistor of fixed value 27; The

other pathrenergizes;the-secondcontrolcircuit 10 through aresistance-enetwork :SU Which' is'not-Qf fixed 'value.

The, turnssof. '10'iand ll'are-soproportionecl that if the'valuelrofzsfixednresistor 27= 'is- -greater than that ofthe variableresistance 30, the signal pulse, dividing and passingihrough boththecontrol-circuit 10 and-control circuit 11,? which it- :Will-be---recalledare connected in' opposition icauses A to fltp't-Conversely, if the value of 30-:exceedsx.that-of 27- 'th'e=signalimpulse causes A to assumesthe flop-condition; If thevalue of thevariable resistor could becaused to increase and to decrease alter-'na'tely: with each' 'successive pulse signal, A could-be made tozflipkandi fio'p rwitli -alternateincoming signal impulse.

This I acco1i1plisl1- .2.by employing-for the variableree sistance- 30a=non linear'resistance element. It is-well known that many types -ofboundary layer devices such as are-:emplo'yed iiiudiy type-or contactrectifiers exhibit marked noni-liii'ear characteristics;- I,'theref0r;Show in" tween themselves and direct current circulates therethrough. Asa result, neglecting filterable efiects, no voltage, eitherunidirectional or alternating, will appear at the short-circuited D.-C.terminals, as a result of the A.'-C. energization of 30.

Between these terminals there will exist nevertheless a resistancevalue; and because of the non-linear characteristic of the selenium orother element used, this resistance will be relatively high if there islittle or no current flowing, and very considerably lower if the twostacks are energized with alternating current so that a substantialdirect current flows through the short-circuit path. The path lyingbetween the two pairs of conjoined D.-C. terminals is considered toconstitute the variable resistance.

The value of this variable resistance has to be controlled at will toproduce the desired result. This can be readily done by appropriatelyenergizing this non-linear network with alternating current. The basisof the method of connecting the two rectifier stacks is that thisarrangement results in decoupling between the A.-C. and the D.-C.circuits, as in a magnetic amplifier. The network 30, of course, is notintended to act as an amplifier and does not do so. But no voltagesemanating from the source from which the non-linear network is energizedappear in the signal input circuit.

Accordingly, the non-linear network 30 is connected to binding posts 24,25 so as to be energized by means of the A.-C. output of flip-flop B.Any time that B is in the flip condition a substantial A.-C. currentflows through 30 whereby the resistance presented to the component ofthe signal impulse passing therethrough is lower than that of the fixedresistor 27. However, when B is in the flop state, in accordance withthe characteristics hereinbefore designated in reference to theflip-flop B, in which the output thereof is reduced to zero, there willbe no energization of the network 30. Thus the resistance presented tothe por tion of the signal impulse which passes through and 30 will besubstantially increased as a result of which the current in 27 will begreater than that in 30, whereat A will be flopped.

Referring now to flip-flop B, as previously indicated, it is desiredthat B should flip and flop in inverse sense in direct response to thetransfer of A from the flip to the flop condition or vice versa. Byhypothesis, the flip-flop B, has similar characteristics to those of A;that is to say it is responsive to control impulses of alternatelyreverse sense. The output of the flip-flop A, it is to be noted,isvariable in magnitude but it is not reversible in sense or polarity.Accordingly, I provide the desired controlling effect upon the flip-flopB by connecting the output binding posts 4, 5 of A to the controlbinding posts 17, 18 of B so that the rectified current from the outputof A energizes the control element 21 of B in the sense which tends tocause the latter to assume the flop condition. The energization of 21,accordingly, will have high value when A is flipped and a value when Ais flopped which will still be of the same sense, but will be reduced inmagnitude. I therefore provide also the bucking or opposing controlelement 20 which latter I energize, in the sense which tends to cause Bto flip, with a predetermined constant magnitude intermediate betweenthe high and low values of the energization of 21. Thus when A is in theflip condition sothat 21 receives the high output current, the effect of21 is greater than that of 20; accordingly the resultant efiect of 20and 21 is in the sense which tends to cause B to assume the fiopcondition. Again, when A is flopped so that the energization of 21 isreduced, 20 preponderates and the net effect is to cause B to flip.

It will be evident to those skilled in the art that the chain ofresponse action above described will produce the desired result. Let itbe assumed for example that the system of Fig. 1 be at rest with Aflopped. Under this condition B is flipped and is energized with A.-C.Suppose now a single control orcount pulse is delivered at 22,

opposite efiect.

23; the resistance of 30 being low the effect of 3 0 exceeds that of 27and A is flipped; whereat B is instantly flopped, de-energizing 30. Itis evident that a second pulse of the same character as the first onewill now produce the A third pulse will find the system in the conditionpostulated at the commencement of the present paragraph and thealternately opposite response will evidently result in respect to allsucceeding pulses.

The operation of a single binary element has now been completelydescribed and explained. However, if such a system is to be used fordigital counting purposes, the circuit must emit a signal of the samecharacter as that by which it is actuated.

I show in Fig. 1 structure for accomplishing this result. I connect tothe binding posts 14 and 15 an output type transformer 16. It will berecalled that rectified output from the flip-flop B is derivable fromthese binding posts. This D.-C. output current, varying between the flipvalue and the zero flop value is demodulated and clipped by thetransformer 16, a capacitor 31 and a half-wave rectifier 34, accordingto the manner well understood by those skilled in the art. I show alsoin Fig. 1 binding posts 32, 33 to which the transformer 16, capacitor 31and half-wave rectifier 34 are connected, thus furnishing at 32 and 33at one-half the count frequency, unidirectional uniform pulses of theidentical character to those supplied at binding posts 22 and 23 bymeans of which my invention, according to Fig. l, is actuated.

I show, in more complete detail, in Fig. 2 an embodiment of my inventionin which flip-flops A and B comprise bi-stable magnetic amplifierelements. Magnetic amplifier flip-flops are well known to those skilledin the art. For example, a bi-stable magnetic amplifier circuit isdisclosed by the present inventor in U. S. Patent 2,027,312. I wish itto be particularly understood that the arrangements disclosed in Fig. 2are shown by way of example only. Any desired type of magnetic amplifierflip-flop may be employed in practicing my invention. I show in Fig. 2some of the more simple arrangements in order to facilitate de scriptionand explanation of the manner of working of my invention. Morecomplicated types of magnetic amplifier, capable of higher speeds ofresponse, are well known in the art.

In Fig. 2 I show A.-C. source 1, flip-flop A and B, fixed resistor 27and non-linear network 30 all as shown and described in reference toFig. 1 and bearing like reference numerals. I show also input bindingposts 22 and 23,

transformer 16, capacitor 31, half-wave rectifier 34 and output bindingposts 32, 33. Referring to flip-flop I show a pair of magnetic cores 35,36 carrying windings 37, 38. The magnetic cores 35, 36 preferably of amagnetic material furnishing an approximately square hysreferencenumerals, these are not repeated for both of the units of each pair ofwindings. It is to be understood that i the winding which is directlyconnected to a winding to which the numeral is appended, is intended tobe likewise referred to thereby. Arrows are appended to each individualwinding indicating the sense of the M. M. F. set up by the currentflowing therein in accordance with the operation of my invention. M. M.F.s are in the same direction for each pair of windings.

Of the four windings shown on the cores 35, 36 the, pair 40 correspondsto the control element 10 in Fig. 1 and the pair 41 corresponds infunction to the control element 11 in Fig. 1. Pair 42 comprises thefeedback winding. The windings 43 comprise the bias, the tune- It willbe noted that the tionl-pf..-twhi hvi ztwell un rstoodbxihaseeskilledninrthez t:.ndwrequires-ronlygunidireetionalexcitation;ottaesube utia-lly, constantmagnitude I,.sho w;also in, Fig, 2 .-a-pair, of,-half.-waverectifiersu-44 and..45 ;to which.wind;ings, 37 and.38;are connected, It;

will be apparent, to. thos e..skilled in the. art pertaining to.

ing; .po.st-,46,, and 'thecorrespondingextremity of winding38fconnectshwithbinding .post 48. Thus the. output circuitofffiip-liopA, including the feedback winding .42 and the.

control element 21"of B',.deriv.es from thejunction pointof half-waverectifiers 44,45 and returns to binding post 47.

Referring to' fiip-fi'o'p B; I shown pair. of 'similar toroids orothencores 55, 56jcarrying A.-C'..windings 57 and 58. I show also threepairs ofDT-CJ" windings 60', 61,62. Pair'60correspondsto winding 20 inFig. l and pair 61' corresponds to winding 21 in Fig; 1. Pair 62 is thefeed-' back winding.

Ishow also in' Fig. 2a counterpoise impedance 63, the functionof'which'is as follows. As hereinbefore'in'di cated'itis' desired thatthe flop value of the output currentof B bezeno. In'asimple: type ofmagnetic amplifier flipfiopsuch as for example that disclosed inU."S.Patent 2,027,3 12; the flop value is'a current of relatively lowmagnitude; It is a characteristic of magnetic amplifiers of elementaltype that the output current, in the, absence of input, is not zero.This current is'often referred to in the artfas the quiescent current,and there are a number of different methods known to those skilled inthe art for compensating for this quiescent current so as to providethat zero output when there'iszero input. Reference may be madeto theteachings of the present inventor published in A. I. E; E; Transactions,part 1, volume 71, page 7;

These methods are equally applicable to the bi-stable characteristic.That is tosay, the flop current may be treatedjas the quiescent current;Thusl show inFig. 2 the methfodof'compensatio'n which isdisclosedin Fig.1-B ofthe above-cited A. I. El'ETreferencc and which corresponds withFig. 2 of U; S..Patent 2,027,311. Thus the connterpoise,impedance 63correspondsin function to the similar circuit element 55 shown in thepatent.

According-to thisarrangement, which is not of the selfsatura'ting type,I show in Fig.- 2 the two windings 57 and 58 connected in series, inopposite sense, with oneextrernity. f winding 58 connecting withbindingpost 48.. I show an extremity of the counterpoise 63connectingwith-bindingpost,46-.,, Accordingly, .the outputcircuitforzfiip-fiop B deriveszfrom 'thejuncti-onnpoint between; 57. and 63andterminates at binding post 47. Thus the output circuit of fiipl-fi'opB:includes'the-non-linear network 30=and the rectifien 64-,i'the D. -C.output of which latter is connected to supply the feedback winding-62andtheprimary winding;

of transformer-16, Thus, in accordancewith the generalarrangements'outlined in referenceto- Fig. l, flip flop B delivers'A-C:outputtoithe non-linear network 30' and rectified output to transformer16.

As has'been hereinbefore explained, both the bias winding 43 offlip-flop A and the winding 60 of fiip-flQpB'are requiredfto, besupplied witl1.;direct.curreritexcitation of fixcdjiappropr iatemagnitude. Accordingly, in..Fig.. 2, I providerthewindings43sand.60..with;numbers of turns andl conuecttthese windingsin.series,.in the proper. sense." as.indicatedbythearrows in.Fig,, 2. Isupply these winds.- ingswith currentfromarectifier 66,.energizedfrombind-- ing,posts 46..and 48, and Iinclude resistors 67. and.68 inz=series with the D.-C. and A.-C. connectionsof 66for. cur.

rentadjustingpurposes;,.

I show .also.,in1Fi'g., 2.,a filter. .choke connected in serieswith.the.rectified.output..of .the flip-flop B. .to the transformer.16.. Alfilter capacitor. 70 islikewise shown. connected .acrosstthe ,DCvterminals. of the non-linear network 30. The-.functionof bothtof.these circuit. elements, is conventional.

I show also in the dit'gramaseries resistor 59 included a in therectified-output.circuit;of flip-flop A, and a shunt. resistor, 69connected. in .parallelwith the A.-C. terminals of 30; Theselatter.resistorsarenot essential functional elements but may, be.found.convenient in some instances. for trimming or.-adjustment.purposesin the event of impedance incompatibility between.the various circuitcomponents.

The. manner. of operationof the system shown in Fig. 2 is essentially inaccordance with. the explanation and description hereinbefore setforthwith reference to Fig. 1.. Thus, the windings 40,41, in Fig. .2,are identical in function with 10,-11, iir'Fig'. 1; and the windings.60, 61, correspond exactly-with 20,21. In.Fig.2 the rectified outputoffiip-flop A is delivered'between the junction pointof 44; 45, andthe'bindingpost. 47; this corresponds with 4, 5,"in Fig.1: Similarly;the. D'.-C. outputof flip-flop. B is delivered'at binding posts 14, 15,.in. Fig. 1, and,v in Fig. 2, at the connections of 62, 65Ito thetransformer 16. In like manner the A.'-C."output of B is, in Fig. 2,delivered. between the lower A.'-CZ connection of the rectifier 64 andthe junctionpoint of 57' andf631which corresponds with. thebindingposts24, 25,in*Fi'g:1'.

Other details'of the circuitof'FigZ Pfirtain to the partic, ular typeoffiip-flop employed, rather than forming. a part. of my inventionper.se, and'are includedonly by wayofi illustration.

I-show in Fig. 3a block diagram depicting how three. binary systems, inaccordancewith the circuit of Fig. 2, would be connected together forapplication in the field of digital computing and. scaling. .Such anassembly would give a count. ofeight. The methods of adapting. largernumbers of binaries to count in decades are well understood by thoseskilled in .the art pertaining to digital computers.-

Thus inFig'. 3 I'show'A.'-C. supply 1, transformer 50, as in Fig.2, and-at:71',72;'and 73, three complete binary systems comprisingsubstantially all. of the structure disclosed and described in'reference-to Fig. 2..

The three binaries 71, '72, and 73"are depicted in block diagramform,and showypertaining to each of the three rectangles representinga'complete'binary, binding posts 22 and 23 for receiving the inputpulse, binding posts 32 and 33-for delivering the. output pulse, andbinding posts 46, 47-, and 48; energizedfr'omthe transformer 50.

As shown in Fig: 3,"thev output'binding posts 32 and 33 of thebinary*=71are connected to the input binding A posts22 and '23 of 72."Thus, assuming a series ofcount signals to be"de1ivered"to the input of71, impulses of one-half' of that frequency are delivered by 71 to 72.

Inlike manner-the output of 72 is connected to the input of 73andsdelivers thereto impulses of one-quarter the'originalcountfrequency.

:priorrart and-;the.: spiritzofnthe appended-claims.

9 What I claim as new and desire to secure by Letters Patent of theUnited States is:

1. A binary counter comprising a first and a second bistableelectroresponsive system, each having two stable operating states, thetwo states of each giving different characteristic output energy, meansfor causing said firstbi-stable system to control in inverse sense saidsecond bi-stable system, a source of control impulses, means connectingsaid impulse source to control said first bi-stable system; meansconnecting said second mentioned bi-stable system with said connectingmeans, whereby alternate control impulses produce opposite effects uponsaid first bi-stable system in accordance with the condition ofstability of said second bi-stable system.

2. A binary counter comprising a first and a second bi-stableelectroresponsive system, each having two stable operating states, thetwo states of each giving different characteristic output energy, meansfor causing said first bi-stable system to control in inverse sense saidsecond bi-stable system, a source of control impulses, means connectingsaid impulse source to control said first bi-stable system, decouplingmeans connecting said second mentioned bi-stable system with saidconnecting means, whereby alternate control impulses produce oppositeeffects upon said first bi-stable system in accordance with thecondition of stability of said second bi-stable system.

3. A binary counter comprising a first and a second bistable system,each having two stable operating states, the two states of each givingdifferent characteristic output energy, means for causing said firstbi-stable system to control in inverse sense said second bi-stablesystem, means for channelling a series of control impulses to said firstbistable system, means connecting said second mentioned bi-stable systemwith said channelling means, whereby said control impulses producedifferent effects upon said first bi-stable system in accordance withthe condition of stability of said second bi-stable system, and meansfor excluding energy from said second bi-stable system from said firstbi-stable system.

4. A binary counter comprising a first and a second magnetic amplifier,each having two stable operating states, the two states of each givingdifferent characteristic output energy, means for causing said firstmagnetic amplifier to control in inverse sense said second magneticamplifier, means for supplying a series of control impulses to saidfirst magnetic amplifier, and means connecting said second mentionedmagnetic amplifier with said supplying means, whereby said controlimpulses produce different effects upon said first magnetic amplifier inaccordance with the condition of stability of said second magn t mplifie5. A binary counter comprising a first flip-flop and a second flip-flop,means whereby when said first flip-flop is flipped said second flip-flopis caused to flop, and whereby When said first flip-flop is fiopped saidsecond flip-flop is flipped, and pair of bridge-type rectifiers havingtheir A.-C. connections paralleled and having their D.-C. outputsconnected in series additively to form a closed circuit, means includingsaid rectifiers for supplying a series of count signal impulses to saidfirst flip-flop, means for deriving A.-C. output from said secondflip-flop, and means for energizing said rectifiers with said A.-C.output.

6. A binary counter comprising a first bi-stable system and a secondbi-stable system, each of said bi-stable systems having two conditionsof stability a high output condition and a low output condition, meanswhereby when said first bi-stable system is in the high output conditionsecond bi-stable system is caused to assume the low ontppt condition andwhereby when first bi-stable systcm in the low output condition saidsecond bisitaiaie system is caused to assume the high output condition,5 pair 01' bridge-type rectifiers having their A.-C. connectionsparalleled and having their D.-C. outputs connected in series additivelyto form a closed circuit, means including said rectifiers for supplyinga series of count signal impulses to said first bi-stable system, meansfor deriving A.-C. output from second bi-stable system, and means forenergizing said rectifiers with said A.-C. output.

7. A binary counter comprising a first bi-stable system and a secondbi-stable system, each of said bi-stable systems having two conditionsof stability, a high output condition and a low output condition, meansfor causing said first bi-stable system to control, in inverse sense,said second bi-stable system, a pair of bridge type rectifiers havingtheir A.-C. connections paralleled and having their D.-C. outputsconnected in series additively to form a closed circuit, means includingsaid rectifiers for supplying a series of count signal impulses to saidfirst bistable system, means for deriving A.-C. output from said secondbi-stable system, and means for energizing said rectifiers with saidA.-C. output.

8. A binary counter comprising a first and a second electricalamplifier, each having two stable operating states, the two states ofeach giving different characteristic output energy, means for causingsaid first electrical amplifier to control in inverse sense said secondelectrical amplifier, means for supplying a series of control impulsesto said first electrical amplifier, and means con necting said secondmentioned electrical amplifier with said supplying means, whereby saidcontrol impulses produce different effects upon said first electricalamplifier in accordance with the condition of stability of said secondelectrical amplifier.

9. A binary counter comprising a first and a second electricalamplifier, each having two stable operating states, said first amplifierhaving a high output condition and a low output condition and saidsecond amplifier having a condition furnishing an output and a conditionfurnishing zero output, means derived from the output of said firstelectrical amplifier to control in inverse sense said second electricalamplifier, means for supplying a series of control impulses to saidfirst electrical amplifier, and means connecting said second mentionedelectrical amplifier with said supplying means, whereby said controlimpulses produce different effects upon said first electrical amplifierin accordance with the condition of stability of said second electricalamplifier.

10. A binary counter comprising a first and a second electricalamplifier, each having two stable operating states, the two states ofeach giving different characteristic output energy, said first amplifierfurnishing unilateral output, said second amplifier furnishing bothunilateral and alternating output, means for causing said firstelectrical amplifier to control in inverse sense said second electricalamplifier, means for supplying a series of control impulses to saidfirst electrical amplifier, variable means included in said supplymeans, and means for energizing said variable means from the alternatingoutput of said second amplifier, whereby said control impulses producedifferent effects upon said first electrical amplifier in accordancewith the conditionof' stability of said second electrical amplifier.

11. A binary counter comprising a first and a second electricalamplifier, each having two stable operating states, the two states ofeach giving difierent characteristic output energy, said first amplifierfurnishing unilateral output, said second amplifier furnishing bothunilatoral and alternating output, means for causing said firstelectrical amplifier to control in inverse sense said second electricalamplifier, means for supplying a series of control impulses to saidfirst electrical amplifier, variable means included in said supplymeans, means for energizing said variable means from the alternatingoutput of said second amplifier, whereby said control impulses producedifferent effects upon said first amplifier in ac;- cordance with thecondition of stability of said second amplifier, and means for derivingfrom the unilateral output of said second amplifier a series of controlimpulses ofi-zthe-same character asusaidl'firststmentioned :series xof12. Aibinary -.counterivcomprisingsa:= first bi-stable: :ele'c tricalsystem and a second bi-stable electrical system each of saidsystemshaving-two conditions-'ofstabllity a high output condition and a lowoutput condition, 1 means for causing said first bi-stable: systemto-control in inverse sense said second bi=stable systemg means-forderiving A;-C. output from said second bif-stabl'e system, means fordelivering a series of count signal impulses to said first bi-stablesystem, and. means for energizing said delivering means Withsaid AL-C,output, said delivering means consisting .ofaa network of rectifierelements so connected together: as to pass said signal impulses to saiddelivering means" with::said A.-C. output, said delivering meansincluding anetwork of variably unilaterally condncting 'eleinentsconnected togeth'er so'asato effect decoupling between said A.-C. outputenergy'and sa'id first bi-stable system.

14. A binarycounter comprisinga first bi-stabIe electrical system and asecond: bi-stable electrical system each of said systems having twoconditionsof stability a high output condition and'a' low outputcondition, means for causing said first bi-stable system to'control ininverse sense saidsecond bi-stable system, means for deriving AJ-C.output'from'said second bi-stable system, means for delivering aseriesof count signal impulses to said first bi-stable system; andmeansfor'energizing said delivering meanswith saiclu'A.-C output, saiddelivering means 'includinganetw'ork of variably conductingelementspermitting'passagemf said signal impulses: to said firstbi-stable system but excluding said 'A.-C. energy therefrom.

ISJAbinary counter comprising a firstbi-stableelectrical system" and asecond bi-stable electrical system each of said systems havingrtwoconditions. of stability a high output'conditionand'azlow outputcondition, means for causing sa'id"first:bi-stable system to control ininverse'sensesa'id secondbi-stable systemrmeanszfot' deriving A.-C.outputlfrom'said second .bi-stable 'system, means'for delivering aseriesfofscount signalimpulsesvto said 'fir'st bi=stable systempandmeans for: energizing saiddelivering meanswith said 1A.-C.. output, said'deliverlng means includingrivariable. impedance means. .for permit--ting passageoftsaid5 signal. impulses to said first" bi-stable systembutexcludingsaid'Az-G energy therefrom;

' I2 163 A binary counter 'comprisin'g 'a" fifst' bi stable electricalsystem and a second bi stable electrical system each :Zoft'sa'id systemshaving two condi'tion's' ot stability aL-high output condition and: a"low'"outp'ut' condition,

means for 'causing said first bi-stable system to contfol in=inversesense said second bi-stable sys'tem, means-tor deriving A'J-C. outputfrom said se'cond*-bi stable sy'stelrd means .7 for delivering aseries-of count signal impulses: to said first" bi-stable system;- andmeans 'for' 'energizing said delivering means with said'A-C.output',-said delivering 3 means including non-linear resistance meanseifecting 'de-" coupling between said A.-C. outputenergy and saidfirstbi-stable system:

17. A binary counter comprisinga first bi-stable' elec trical systemand'a second"bi stable electrical system each of isaid systemshaving-two conditions of'st'ability" a high'aoutput condition and a lowoutput condition;- m'ean's -for causingsaid'first bi stable system' 'toconti'ol inv inverse sense said secon'd bi-stablesystem, means forderivingA-C. output from said second bi-stable' system; I means fordelivering a seriesof count signal impulses to said first bi-stablesystem, and means for energizing said deliveringmeans with said-Arc.output, said'deliverin'g meansincluding non-linear attenuating-meanseffecting decoupling between said A.-C. output energ'yand said" firstbi-stable system.

18. A- binary counter comprising a first'bi-stable electrical system anda second bi-stable' electrical system each of said systems having twoconditions of stability a highoutput-condition and a low outputcondition, means for causingsaid first bi-stable system to controlin'inverse sense' said second bi-stable system, means for deriving AeC.output from said second bi-sta'ble system,

means for delivering a series of count signal impulsesto I said'fir'st'bhstable system, and means for energizing said deliveririg'meanswith said A.-C.output, said delivering means including semi-conductormeans effecting decoupling between said A.-C. output energy.andsaid'first" bi-stable system.

19;A digital counter-comprising a first and a second electroresponsivesystem each having a plurality of stable operating conditions givingdiffering output magnitudes, means'for causing said first system tocontrol in inverse sense said second system, means for deriving A.-C.outputf'rom said second system, means for supplying a series ofcountsignal impulses to said first 'electroresp'onsive systennmeans for'energizing'said supplying means with said An-C. output; saidsupplyi'ngmeans including controllable' variably transmitting means permittingdelivery of said'count signal impulses to saidfirst electroresponsive'system but excluding therefrom said A.-C. output energy from saidvsecondelect-roresponsive system.

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